The invention relates to systems and methods for operating a computing system in response to an interrupting peripheral device.
Various sytems and methods have been utilized to operate a computing system in response to an interrupting peripheral device. One known system includes an interrupt conductor connected to the input of a processor and connected to an interrupt output of all peripheral devices of the system. The processor responds to an interrupt request signal on the interrupt conductor by vectoring to a software polling subroutine. The polling subroutine polls the peripheral devices of the system by addressing each of them in a prioritized order to determine which peripheral device generated the interrupt request. Once the processor determines, by means of the polling operation, which peripheral device produced the interrupt request, the processor refers to a stored table to obtain the address of the appropriate interrupt request service subroutine. However, use of software polling systems to establish priority of interrupting peripheral devices is unsatisfactory for a system such as a typical industrial control system which has a large number of peripheral devices, because of the large amount of time required to poll all of the peripheral devices every time an interrupt request signal is generated by the equipment being controlled by the computing system. This is especially true in a system which is operating at a speed close to its maximum speed. Industrial control systems typically do operate at a rate close to their maximum rate because relatively inexpensive, low speed microprocessors, memories and associated logic circuitry are utilized.
Another type of commonly utilized interrupt scheme is referred to as a "daisy chained" interrupt system. In a daisy chained interrupt system, the peripheral devices are serially connected so that if one of the peripheral devices generates an interrupt request signal, the processor produces an "acknowledge" signal which is provided as an input to the highest priority peripheral device. Each peripheral device gates the acknowledge signal to the next peripheral device if the first peripheral device is not the one which produced the interrupt request signal. The peripheral devices are sequentially connected in order of the priority of their respective interrupt request signals. The daisy chained interrupt system may identify the interrupting peripheral device more rapidly than a polled interrupt system, but has the disadvantages that if a particular peripheral device is removed from the system for some reason, the prioritizing system becomes inoperative, and the system further requires additional gating circuitry to be incorporated in each peripheral device.
Other interrupt techniques involve multiple interrupt lines, one from each peripheral device, connected to a priority encoding circuit which immediately generates the address of the appropriate interrupt service subroutine. Such systems require the interrupt service subroutine to generate the address information necessary to select the interrupting peripheral device to enable it to communicate with the processor. Such systems therefore require a great deal of hardware (multiple inerrupt lines and address generating circuitry) and additional software to select and enable the interrupting peripheral device.
Certain data processing systems, including typical industrial control systems, need to be able to operate utilizing relatively slow, inexpensive microprocessors and peripheral devices. Such systems typically involve very large numbers of peripheral devices. Such industrial control systems therefore are not well suited for utilization of software priority determining polling routines, and further need the flexibility of being capable of operation when one or more peripheral devices are temporarily removed, and usually must be implemented at minimum cost, and therefore are not well suited to any of the above types of interrupt systems.
There exists a need for an interrupt system which rapidly established priority of interrupt requests from peripheral devices in a minimum amount of time, utilizing less hardware than known priority interrupt systems, while placing a minimum software burden on the system programmer.
The following patents are believed to generally indicate the state of the art for priority interrupt systems and methods: U.S. Pat. Nos. 3,208,048; 3,675,209; 3,710,324; 3,828,325; 3,909,790; 3,924,240; 4,003,033; 4,020,472; 4,027,290; and 4,037,204.